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Set lr correctly in blx esil on arm #22377
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Uhm is your branch based on master? |
oops nope. 5.8.8, will rebase |
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i think the problem is that the program counter results in an unaligned address,and the proper behaviour here would be to remove the lower bit and set the thumb mode flag instead |
This and the issue may have been a misunderstanding, I've updated to a build from master and some things have changed or been solved already; issue I'm trying to solve now is -
where the instruction's esil is:
Stepping over again, behaves as expected, though. Is this expected? Naturally I can make this go away with |
Sorry for the late response. kinda busy irl :( let me try to give you a proper response here. It's been a while since i really do some thumb/arm binary analysis, and i think it's been always a pending task to be addressed.. and maybe it's the time to do so if you are in the mood to discuss and test things. I'm not sure the way it works right now, or how it should be working, but basically the way that ARM switches between thumb and arm modes is depending on the lower bit of the program counter which maps to the thumb bit of the cpsr register. So, i see different things there that must be clarified before moving further.
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Description
see #22373